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Chapter 1: What’s New in ISE Design Suite
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AXI Interconnect LogiCORE IP v1.03.a connects one or more AXI4 memory-
mapped master devices to one AXI4 slave device. The AXI interconnect
supports address widths from 12 to 64 bits with interface data widths of 32,
64, 128, 256, 512, or 1024 bits. Users can now implement a DDR2 or DDR3
SDRAM multi-port memory controller using MIG and AXI Interconnect IP
from CORE Generator.
AXI Bus Functional Model (BFM) v1.9 solution, created for Xilinx by
Cadence? Design Systems, enables Xilinx customers to verify and simulate
communication with AXI-based IP that is being developed. The AXI BFM IP
in CORE Generator delivers test-benches examples and script examples that
demonstrate the use of the BFM test writing APIs for AXI3, AXI4, AXI4-Lite,
and AXI4-Stream masters and slaves.
AXI Direct Memory Access (DMA) LogiCORE IP v4.00.a provides a flexible
interface for transferring packet data between system memory (AXI4) and
AXI4-Stream target IP. The AXI DMA provides optional support of
Scatter/Gather for off-loading processor management of DMA transfers and
descriptor queuing for pre-fetching transfer descriptors to enable
uninterrupted transfer requests by the primary DMA controllers.
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Audio, Video, and Image Processing IP
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Video Timing Controller v3.0 now supports AXI4-Lite interface and Virtex-7,
Kintex-7 device family
Triple Rate SDI has introduced support for Spartan?-6
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DSP Building Blocks
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Floating-Point Operator v6.0 now supports AXI4-Stream interface, two new
operators reciprocal (1/x) and reciprocal square root (1/sqrt(x)), bit accurate
C-model and VHDL test bench
CIC Compiler v3.0 now supports AXI4-Stream interface and VHDL test
bench
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Standard Bus Interfaces and I/O
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32-bit and 64-bit Initiator/Target for PCI now supports Virtex-7 and Kintex-7
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Additional IP supporting AXI4 Interfaces
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The latest versions of CORE Generator IP have been updated with Production
AXI4 interface support. For more detailed AXI IP support information see
www.xilinx.com/ipcenter/axi4_ip.htm .
In general, the AXI4 interface is supported by the latest version of an IP, for
Virtex-7, Kintex-7, Virtex-6 and Spartan-6 device families. Older "Production"
versions of IP continue to support the legacy interface for the respective core on
Virtex-6, Spartan-6, Virtex-5, Virtex-4 and Spartan-3 device families only.
For general information on Xilinx AXI4 support, see
www.xilinx.com/ipcenter/axi4.htm .
A comprehensive listing of cores that have been updated in the Release 13 can be
viewed at www.xilinx.com/ipcenter/coregen/updates_13_1.htm .
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PlanAhead IP Design Flow Enhancements
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Enhancement added to inform user about availability of updated versions of IP
used in their design.
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www.xilinx.com
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
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